library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity userControl is
  port(clk, i_up, i_down, i_left,i_right : in std_logic;
       out_concat : out std_logic_vector(19 downto 0)); --horizontal: 19 downto 10, --vertical: 9 downto 0);
end userControl;

architecture Control of userControl is

signal currentH : std_logic_vector (9 downto 0) := "0101000000"; --set to 320 (center)
signal currentV : std_logic_vector (9 downto 0) := "0011111111"; --set to 255

begin
	process (clk)
	begin
		if (rising_edge(clk)) then
		
			if (i_up = '1') then
				currentV <= currentV - "0000000001";
			end if;

			if (i_down = '1') then
				currentV <= currentV + "0000000001";
			end if;
			
			if (i_left = '1') then
				currentH <= currentH - "0000000001";
			end if;

			if (i_right = '1') then
				currentH <= currentH + "0000000001";
			end if;
			
			--Restrictions
			if (currentH < conv_std_logic_vector(115,10)) then
				currentH <= conv_std_logic_vector(115,10);
			end if;

			if (currentH > conv_std_logic_vector(525,10)) then
				currentH <= conv_std_logic_vector(525,10);
			end if;
			
			if (currentV < conv_std_logic_vector(45,10)) then
				currentV <= conv_std_logic_vector(45,10);
			end if;

			if (currentV > conv_std_logic_vector(255,10)) then
				currentV <= conv_std_logic_vector(255,10);
			end if;
			
		end if;
		
	end process;
			
	out_concat <= currentH & currentV;

end architecture Control;